The Design-for-Test (DFT) methodology is a strong driving force in the cost-effective testing of large-volume commodity items with very short life cycles, like system-on-chip (SoC) devices. It will ...

As the demand for processing power for artificial intelligence (AI) applications grows, semiconductor companies are racing to develop AI-specific silicon. The AI market is incredibly dynamic, with ...

Over the last few years, design-for-test (DFT) chip-testing techniques such as internal scan (ISCAN), automatic test-pattern generation (ATPG), built-in self-test (BIST), and boundary scan (BSCAN) ...

The dramatic rise in manufacturing test time for today’s large and complex SoCs is rooted in the use of traditional approaches to moving scan test data from chip-level pins to core-level scan channels ...

BALTIMORE — The marriage of design-for-test (DFT) software with test hardware may drastically lower the cost of test, according to several companies that will present their plans at this week's ...

To meet the increasing size of ICs, required to accommodate the integration of billions of transistors in order to deliver the performance required for tasks such as AI and autonomous vehicles, Mentor ...

Back when semiconductor devices contained only a few thousand gates, manufacturing test was almost an afterthought. The development team threw the chip “over the wall” to the test engineers, who ...