While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...

A well thought out design flow for SoCs ensures that the resulting device meets the requirement of low power dissipation. To meet these goals at the device level, individual modules (or components of ...

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...