EDN

Chain debugger said to cut circuit debug, test times

SAN FRANCISCO — Boundary scan development tool supplier XJTAG has added a JTAG chain debugger to its XJTAG Development System, which will further reduce debug and test times for engineers designing ...
Electronics Weekly

Taking the bug out of FPGA debugging

Design verification has emerged as one of the most time-consuming aspects for systems based on FPGA, particularly as the design size and complexity continues to grow. Contributing aspects to the ...
EDN

Advances in on-chip serial debugging

http://www.motorola.comDeveloping and testing software has become the major slice of many embedded systems development budgets. Therefore it should be no surprise ...
Design-Reuse

Analog Circuit Works Adopts Diakopto's ParagonX Platform for High-Performance Analog Circuit IP

San Jose, CA -- September 14, 2021 -- Diakopto announced today that Analog Circuit Works, a premier provider of System on Chip (SoC) and analog circuit IP, has selected the ParagonX debugging and ...
Design-Reuse

Communication centric test and debug infrastructure for multi core SoC

The integration and debug of multiple cores, combined with an increasing ratio of overall gates vs. package IO, makes an increasingly dominant amount of a system design "“deeply embedded†, such ...